The use of an access device with a storage element in memory cells is well known in the art. Examples of memory devices that utilize access devices include dynamic random-access memory (DRAM), resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), and phase-change random-access memory (PRAM).
An ever-increasing demand for higher-density memory cell arrays has lead to the development of vertical memory cell devices. Vertical memory cell devices may enable higher-density cell arrays by offsetting an access device vertically from a storage element, which arrangement utilizes less horizontal area, termed “real estate,” on the array substrate than if the access device were offset horizontally from the storage element.
FIG. 1A is a simplified plan view of a portion of a conventional memory cell array 100. The conventional memory cell array 100 includes a plurality of vertical memory cells 101, a plurality of data/sense lines 104, e.g., digit or bit lines, (in dashed lines to show they are buried), and a plurality of access lines 114, e.g., word lines (in dashed lines to show they are buried). The vertical memory cells 101 are arranged in rows (coupled to a common digit line 104) and columns (coupled to a common word line 114). Individual vertical memory cells 101 are located at a cross-point of a digit line 104 and a word line 114.
FIG. 1B is a simplified cross-sectional view of a vertical memory cell 101 taken along line 1B-1B of FIG. 1A. The vertical memory cell 101 may be formed on a substrate 102. The vertical memory cell 101 includes a storage element 110 and an access device such as a transistor. The vertical memory cell 101 includes a digit line 104, a body region 106 disposed on the digit line 104, an electrode 108 disposed on the body region 106, a word line 114 proximate to the body region 106, and a storage element 110 (e.g., a capacitor) disposed on the electrode 108. The vertical memory cell 101 also includes a dielectric material 112 on the substrate 102, and surrounding the vertical memory cell 101. The dielectric material 112 insulates the body region 106 from the word line 114.
The vertical memory cell 101 is configured to establish electrical connection and isolation between the digit line 104 and the storage element 110. In other words, the digit line 104, the body region 106, and the electrode 108 from an access transistor, with the word line 114 functioning as its gate. In use and operation, a first voltage is applied to the word line 114, which may attract charge carriers to a segment of the body region 106 that is proximate to the word line 114. As a result, a conductive channel 116 (in dashed lines to show intermittent presence) may be formed through the body region 106 between the digit line 104 and the electrode 108. The conductive channel 116 enables the digit line 104 to access the storage element 110 for read or write operations.
If the first voltage is removed from the word line 114, the conductive channel 116 may be removed, electrically isolating the storage element 110 from the digit line 104. As a result, by selectively applying the first voltage to the word line 114, electrical connection and isolation between the digit line 104 and the storage element 110 is established. In addition, different combinations of voltages may be applied to the word line 114 and the digit line 104 to select a particular vertical memory cell 101 from the conventional memory cell array 100 for a read or write operation.
Although the vertical memory cell 101 may successfully establish electrical connection and isolation between the digit line 104 and the storage element 110, the body region 106 is a floating body. Consequently, the vertical memory cell 101 suffers from floating body effects, which may result in degraded charge retention time in the case of DRAM devices, and power distribution problems in the conventional memory cell array 100.
Conventional solutions to reduce floating body effects often require additional processing acts and consume increased surface area of the memory array for a given number of memory cells. For example, a bias voltage that is different than a voltage applied to the conductive lines (e.g., digit lines, word lines, etc.) may be applied to the vertical memory cells 101 to reduce floating body effects. However, connecting the vertical memory cells 101 to the bias voltage may require complex processing acts such as complex lithographic techniques and may increase the surface area for the semiconductor device. It would, however, be desirable to reduce or eliminate the floating body effects of vertical memory cells without significantly increasing the number of processing acts and array surface area.